Are you an expert digital design and verification engineer with 7+ years experience developing mixed-signal chips? Do you want to play a key role in building next generation Wi-Fi chips that will truly enable the Internet of Things? Keen to make a real difference in a VC-backed startup and work in a dynamic & fun environment? Then join Australia’s fastest growing semiconductor company based in Sydney. You’ll work with the team that invented Wi-Fi 20 years ago, and help shape the future of Wi-Fi.

As a Senior Digital Design and Verification Engineer, your responsibilities will include the design, development, and verification of digital subsystems within our chips. Ideal applicants will have a broad range of digital design and verification skills and strong industry experience in designing low-power mixed-signal SoCs. 

We are open to sponsoring a work visa for the right candidate.

Responsibilities include:

• Chip and block-level design and verification
• Enhancement of our design and verification infrastructure
• Working across teams to ensure efficient hardware-software co-design and implementation
• Assisting with tapeout duties such as system verification, synthesis, ensuring excellent QoR in P&R, gate level netlist simulations to validate design and power intent, and power analysis 

What we’re looking for:

• Digital design and verification experience with 7+ years relevant industry experience
• MSc in Electrical / Electronics / Communication Engineering or Computer Science
• A deep understanding of digital design fundamentals including low power and multi-clock-domain design for mass-produced, mixed-signal chips
• Expert in mixed signal ASIC design and simulation, experience with AMS simulation is a plus
• Very experienced with the Cadence or Synopsys simulation suites
• Experience with coverage collection tools
• Experience defining functional verification requirements, implementing tests to meet them
• Expert in HDL languages such as Verilog, SystemVerilog or VHDL 
• Experience with building complex testbench infrastructures
• Experience running and debugging gate level simulations in post-PnR netlists with SDF annotation, power-aware simulation experience is a plus
• Experience setting up and maintaining continuous integration (CI) flows for regression testing and reporting status

What we offer:

• Competitive salary + excellent stock option package
• Healthy work environment with sit/stand desks and large screens
• Office perks such as stocked drinks fridge, snack bar and barista coffee
• Newly fitted-out offices, with a relaxed, friendly work environment

How to apply:

To apply submit your CV and cover letter and tell us why you would be a stand-out applicant for the role of Senior Digital Design & Verification Engineer at Morse Micro.